SIGDA E-News 1 April 2012, Vol. 42, No. 04

 Special Interest Group on Design Automation
1 April 2012, Vol. 42, No. 4
Online archive:

  1. SIGDA News
        From: Lin Yuan <>
  2. What is a Body Sensor Network?
        Contributing authors:
        Benton H. Calhoun <> University of Virginia John Lach <>, University of Virginia
        From: Srinivas Katkoori <>
  3. Paper Submission Deadlines
        From: Debjit Sinha <>
  4. Upcoming Conferences and Symposia
        From: Debjit Sinha <>
  5. Upcoming Funding Opportunities
        From: Sudeep Pasricha <>
  6. Call for Papers: International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)
        From: Sudeep Pasricha <>
  7. Call for Papers: International Conference on Very Large Scale Integration (VLSI-SOC)
        From: Matthew Guthaus <>
  8. Call for Papers: ACM Student Research Competition (SRC) at Design Automation Conference
        From: Srinivas Katkoori <>
  9. Call for Papers: Special Issue on Practical Parallel EDA
        From: Rasit O. Topaloglu <>
  10. Call for Abstracts: International Workshop on Bio-Design Automation (IWBDA)
        From: Natasa Miskov-Zivanov <>
  11. Call for Applications: Student Scholarships ACM A.M. Turing Centenary Celebration
        From: Srinivas Katkoori <>
  12. Call for Papers: International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)
        From: Philip Brisk <>

Comments from the Editors

Dear ACM/SIGDA members,

In this issue, we have reprinted a very interesting article on "What
is a Body Sensor network?" If you are interested in contributing to
this column in the future, please contact Srinivas Katkoori
<>. An article only needs to be about 1 page long
with several references. All articles are included in the ACM digital
library and there is no restriction for the reproduction of the
article for printed publication later.

Matthew Guthaus, E-Newsletter Editor;
Debjit Sinha, E-Newsletter Associate Editor;
Lin Yuan, E-Newsletter Associate Editor;
Sudeep Pasricha, E-Newsletter Associate Editor;
Srinivas Katkoori, E-Newsletter Associate Editor

Back to Contents


"'Thermal cloak' to dissipate heat in electronics"
A team of French researchers have found a way of isolating or cloaking
objects from sources of heat by diffusing the heat around the
objects. The “thermal cloaking” method taps into some of the same
principles as optical cloaking and may lead to novel ways to control
heat in electronics.

"Slideshow: EE Times, EDN honor 2012 ACE Award winners"
UBM Electronics, a division of UBM plc and the publisher of EE Times,
EDN and other publications, honored companies, teams and individuals
for achievements over the past year by presenting the 2012 UBM
Electronics ACE Awards in a ceremony here Tuesday (March 27).

"Using virtual worlds to 'soft control' people's movements in the real one"
Eighty-eight percent of Americans now own a cell phone, forming a
massive network that offers scientists a wealth of information and an
infinite number of new applications. With the help of these phone
users — and their devices' cameras, audio recorders, and other
features — researchers envision endless possibilities for gathering
huge amounts of data, from services that collect user data to monitor
noise pollution and air quality to applications that build maps from
people's cell phone snapshots.

"New iPad has higher BoM than iPad 2, says IHS"
Apple Inc.'s new iPad models are more expensive to produce than the
iPad 2 at time of launch, though they carry the same price points,
according to market research firm IHS iSuppli.

"Apple's iPad to dominate NAND use in tablets through 2015"
Apple Inc.'s iPad accounts for nearly 80 percent of the NAND flash
memory used in media tablets and is expected to continue to dominate
worldwide demand for NAND in tablets through at least 2015, according
to market research firm IHS iSuppli.

"Cloud-connected MCUs with out-of-box cloud connectivity"
Digi International announced its collaboration with Freescale
Semiconductor to integrate the secure and scalable iDigi Device Cloud
solution into Freescale's leading Kinetis and ColdFire microcontroller
platforms. Using the iDigi Connector, an open interface for any type
of device, Kinetis and ColdFire customers now have immediate access to
both a web and mobile applications development platform and world
class device management functionality.

"Research project sketches centralized computing architecture for e-cars"
It has become somewhat silent about electric vehicles, and at the
current Geneva Motor Show, e-cars do not take center stage, much in
contrast to the past few years. This silence however is deceptive;
behind the stages, the industry is feverishly working on the design of
this type of vehicles. Recently, a research project has been launched
that gets granular on the software architecture for electric cars -
and it aims to the core of architectural concepts.

"MIT makes Hornet multicore simulator power aware"
Researchers at the Massachusetts Institute of Technology have
developed a software simulator, called Hornet, that they claim models
the cycle-accurate performance of multicore chips and scales up to
1,000 of cores.

Back to Contents

What is a Body Sensor Network?

Benton H. Calhoun and John Lach
University of Virginia

Body sensor networks (BSNs) comprise wearable or implanted sensors
that collect, process, and communicate physiological information from
the body. With healthcare costs soaring, we need a more efficient and
cost effective approach to medical diagnosis, treatment, and
care. BSNs could revolutionize healthcare by offering miniaturized,
unobtrusive, nearly continuous monitors to provide unprecedented
levels of medical observation while simultaneously reducing the need
for visits to the doctor. BSNs provide feedback to users that can
illuminate potential health concerns earlier, encourage healthier
lifestyles, and improve personal wellbeing. There is also the
potential for using the collected data to provide real-time
assessments of an individual's condition and need that could trigger a
real-time assistance mechanism, such as a balance assistive device or
a wearable defibrillator. If adopted widely, this technology could
also upgrade well patient monitoring, enable at home aging and care,
report on medication effectiveness, and cut the costs of healthcare
across the board [Hanson09].

Anatomy of a Body Sensor Network

A BSN consists of one or more sensor nodes that form a communication
network. Usually, one of the nodes acts as a base station, which
aggregates information from the body-distributed sensor nodes and
ultimately conveys it across existing networks to other stakeholders
like the wearer's caretakers and physicians. Smart phones are already
supporting many useful health related apps, and future generation
smart phones are the obvious choice to serve double duty as a BSN base
station. The base station thus plays a different role from the other
nodes in the system, and it has more resources in terms of bigger
size, available energy, longer range radios, and more memory and
computing power. The sensor nodes themselves each contain a set of
sensors for particular physiological data, processing hardware for
computation, and a wireless radio for communication (some BSN nodes
may replace the radio with a transceiver that communicates across the
body, using the surface of the skin as a communication channel
[Barth08]). Based on the application requirements, the sensed data may
be streamed wirelessly or stored locally (typically in a flash memory)
for later transmission or download.

BSNs versus Wireless Sensor Networks

While BSNs hold these basic components in common with generic wireless
sensor networks (WSNs), which have provided a popular research topic
for years, there are several important distinguishing features for
BSNs. First, the body itself prevents the reuse of the same node
across many roles due to the particularities of measuring
physiological data. For example, an electrocardiogram (ECG) sensor
that measures the electrical activity of the heart works well in the
torso area, but it cannot work on the wrist; a gait sensor probably
uses accelerometers and gyroscopes and is best located on the legs;
the sensor on the head that measures brain activity
(electroencephalogram (EEG)) probably cannot also measure respiration
rate. Second, the proximity of the base station and the unique nature
of each node's sensing modality makes node to node communication
largely unnecessary. Instead of the ad hoc network arrangements common
in WSNs, BSNs tend to use a star-hub topology with each sensor node
communicating only with the base station (as the hub). Third, the
number of nodes in a BSN (< 10 for most systems) is smaller than in
common WSNs (> 1000s for large-scale environmental monitoring, for
example), but the per node data rates are typically much higher, with
ECG or EEG data being inherently more dynamic than environmental
temperature data. Finally, the wearable nature of the BSN nodes places
unique constraints on their specification and design to make them
acceptable for widespread use but also provides more regular node
access for maintenance and re-charging.


Specifically, BSN nodes will not be adopted if they are too
inconvenient, uncomfortable, or unsightly. The level of tolerable
clunkiness for a BSN node is proportional to its importance to the
user; I would wear a life saving heart pacer, for example, no matter
how obtrusive it is. On the other hand, if my doctor just wants to get
feedback on the effects of my new heart medication, I probably won't
put up with wearing a pager attached to my chest. To encourage
widespread use of BSNs, system designers must shrink the size of the
nodes to the sub cubic centimeter level and give them conformal,
wearable shapes that disappear to the point that they are forgettable
by the wearer. Such small form factors place a severe limit on the
amount of energy that the node can store locally (e.g., small
batteries). This creates a challenge to provide the necessary
functionality for the desired application within a tight energy
budget. Some BSN nodes could use batteries that are recharged
regularly, for example if the user removes them at night. Other nodes
might need to be used continuously for longer periods, although as
noted above, unlike some WSNs, they are unlikely to be worn for much
more than a week or so before removal for some activities (e.g.,
bathing, sleeping). In an effort to further reduce the node size and
to extend their usable lifetime, some BSN researchers are pursuing
custom solutions that supplement or replace the battery by harvesting
energy from the body environment (e.g., body heat, vibration, solar)
[Calhoun11]. Eliminating the battery through energy harvesting would
shrink the node, make it cheaper, and potentially improve the
possibility of integrating it into items people already wear like
clothing, shoes, or jewelry.

Other Technical Challenges

While the BSN field has made good progress developing systems to sense
data and get it where it needs to go, additional research is necessary
to convert that data into information relevant to the target
application. This requires advancements not only in signal processing
and data mining but also in interdisciplinary collaborations that
involve application domain expertise. In the long run, these
technologies must be demonstrated to improve patient outcomes, enhance
quality of life, and reduce healthcare costs - and the demonstrations
must be through real deployments on real people.

Other technical challenges facing BSNs include security, privacy, and
safety - all of which are essential given the target medical
applications and are made challenging given the severe resource
constraints and dynamic nature of the system and environment. Highly
important research thrusts also include incorporating additional
sensing modalities, providing real-time guarantees (especially for
applications involving actuation), achieving ultra low power
sensing/processing/communication/networking, and realizing usability
across a diverse group of users.

BSNs in Action

BSNs can provide a huge array of applications, both currently
implemented and envisioned for the future. Sensing modalities include
ECG, EEG, EMG, blood pressure, pulse oximetry, motion, etc., enabling
applications ranging from outpatient physiological monitoring [Wong09]
and neurology disorder classification [Xu11] to fall risk assessment
[Lockhart10] and detection [Li11] and closed loop insulin pump
regulation [Clarke09].


In conclusion, BSNs enable a diverse and powerful new direction in
medical care. While technical and societal challenges remain,
promising initial forays in BSN development show the potentially
revolutionary possibilities for this technology. We are confident that
BSNs are coming soon to a body near you.


[Barth08] A.T. Barth, M.A. Hanson, H.C. Powell Jr., D. Unluer,
S.G. Wilson, J. Lach, “Body-Coupled Communication for Body Sensor
Networks,” International Conference on Body Area Networks, 2008.

[Calhoun11] B.H. Calhoun, J. Lach, J. Stankovic, D.D. Wentzloff,
K. Whitehouse, A.T. Barth, J.K. Brown, Q. Li, S. Oh, N.E. Roberts,
Y. Zhang, “Body Sensor Networks: A Holistic Approach from Silicon to
Users,” Proceedings of the IEEE, in press.

[Clarke09] W.L. Clarke, S. Anderson, M. Breton, S. Patek, L. Kashmer,
B. Kovatchev, “Closed-Loop Artificial Pancreas Using Subcutaneous
Glucose Sensing and Insulin Delivery and a Model Predictive Control
Algorithm: The Virginia Experience,” Journal of Diabetes Science and
Technology, Vol. 3, No. 5, September 2009.

[Hanson09] M.A. Hanson, H.C. Powell Jr., A.T. Barth, K. Ringgenberg,
B.H. Calhoun, J.H. Aylor, J. Lach, “Body Area Sensor Networks:
Challenges and Opportunities,” IEEE Computer, January 2009.

[Li11] Q. Li, J. Stankovic, “Grammar-Based, Posture- and
Context-Cognitive Detection for Falls with Different Activity Levels,”
Wireless Health, 2011.

[Lockhart10] T.E. Lockhart, A.T. Barth, X. Zhang, R. Songra,
E. Abdel-Rahman, J. Lach, “Portable, Non-Invasive Fall Risk Assessment
in End Stage Renal Disease Patients on Hemodialysis,” Wireless Health,

[Wong09] A.C.W. Wong, D. McDonagh, O. Omeni, C. Nunn,
M. Hernandez-Silveira, A.J. Burdett, “Sensium: An Ultra-Low-Power
Wireless Body Sensor Network Platform: Design & Application
Challenges,” Annual International Conference of the IEEE Engineering
in Medicine and Biology Society, 2009.

[Xu11] X. Xu, M.A. Batalin, W.J. Kaiser, B. Dobkin, “Robust
Hierarchical System for Classification of Complex Human Mobility
Characteristics in the Presence of Neurological Disorders,”
International Conference on Body Sensor Networks, 2011.

Back to Contents

Paper Submission Deadlines

BodyNets'12 - Int'l Conference on Body Area Networks
Oslo, Norway
Sep 24-26, 2012
Deadline: Apr 1, 2012

DFM&Y'12 - Int'l Workshop on Design for Manufacturability & Yield
San Francisco, CA (Co-located with DAC'12)
Jun 4, 2012
Deadline: Apr 8, 2012

IWBDA'12 - Int'l Workshop on Bio-Design Automation
San Francisco, CA (Co-located with DAC'12)
Jun 4-5, 2012
Deadline: Apr 2, 2012

ASQED'12 - Asia Symposium on Quality Electronic Design
Kuala Lumpur, Malaysia
Jul 10-12, 2012
Deadline: Apr 4, 2012

VLSI-SoC'12 - Int'l Conference on Very Large Scale Integration and System on Chip
Santa Cruz, CA
Oct 7-12, 2012
Deadline: Apr 9, 2012

ICCAD'12 - Int'l Conference on Computer-Aided Design
San Jose, CA (tentative)
Nov 2011 (exact dates to be announced)
Deadline: Apr 16, 2012

Wireless Health'12
San Diego, CA
Oct 22-25, 2012
Deadline: Apr 20, 2012

Back to Contents

Upcoming Conferences and Symposia

ASYNC'12 - Int'l Symposium on Asynchronous Circuits and Systems
(co-located with NOCS'12)
Copenhagen, Denmark
May 7-9, 2012

NOCS'12 - Int'l Symposium on Networks-on-Chip
(co-located with ASYNC'12)
Copenhagen, Denmark
May 9-11, 2012

EWME'12 - European Workshop on Microelectronics Education
Grenoble, France
May 9-11, 2012

BSN'12 - Int'l Conference on Wearable and Implantable Body Sensor Networks
London, UK
May 10-12, 2012

ISCAS'12 - Int'l Symposium on Circuits and Systems
COEX, Seoul, Korea
May 20-23, 2012

DAC'12 - Design Automation Conference
San Fransisco, CA
Jun 3-7, 2012

SLIP'12 - System Level Interconnect Prediction
(co-located with DAC'12)
San Francisco, CA
June 3, 2012

ISCA'11 - Int'l Symposium Computer Architecture
Portland, OR
Jun 9-13, 2012

AHS'12 - NASA/ESA Conference on Adaptive Hardware and Systems
Nuremburg, Germany
Jun 25-28, 2012

MEMOCODE'12 - Int'l Conference on Formal Methods and Models for Codesign
Arlington, VA
Jul 16-18, 2012

PACT'12 - Int'l Conference on Parallel Architectures and Compilation
Minneapolis, MN
Sep 21-25, 2012

Back to Contents

Upcoming Funding Opportunities


Office of Naval Research (ONR) Sabbatical Leave Program
Deadline: N/A

Naval Research Laboratory (NRL) Postdoctoral Fellowship Program
Deadline: Continuous


Microsystems Technology Office-Wide Broad Agency - DARPA-BAA-10-35
Deadline: September 1, 2012

DARPA-BAA-12-24: Power Efficiency Revolution For Embedded Computing Technologies
Deadline: April 16, 2012


Robust Computational Intelligence - AFOSR-BAA-2011-01
Deadline: Continuous

Systems and Software - AFOSR-BAA-2011-01
Deadline: Continuous

ERDC BAA - Computational Science and Engineering (ITL-1)
Deadline: Continuous

Advanced Distributed Sensor Technologies - BAA 57-09-06
Deadline: Continuous

Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01)
Deadline: Continuous

High Performance Computing on Massively Parallel Architectures (BAA 64-09-01)
Deadline: Continuous

ASEE-NRL Postdoctoral Fellowship Program
Deadline: N/A


Postdoctoral Appointments
Deadline: N/A

Sabbaticals and Faculty Appointments
Deadline: continuous

McDonnell Foundation

Studying Complex Systems - 21st Century Science Collaborative Activity Awards
Deadline: continuous


Sustainability Research Networks Competition (SRN)
Deadline: April 1, 2012

Computing Education for the 21st Century (CE21)
Deadline: April 9, 2012

Integrative Graduate Education and Research Traineeship Program (IGERT)
Letter of Intent: May 1, 2012

Cyberlearning: Transforming Education (Cyberlearning)
Letter of Intent: May 14, 2012

Partnerships for International Research and Education (PIRE)
Deadline: May 15, 2012

Back to Contents

Call for Papers: International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)


RTCSA 2012
The 18th IEEE International Conference on Embedded and Real-Time
Computing Systems and Applications

August 20 - 22, 2012
Seoul, Korea

SUBMISSION DEADLINE: Apr 16, 2012, 12:00 (noon) GMT+9

Embedded software has become a necessity in almost every aspect of the
daily lives of individuals and organizations, from self-contained
applications to those embedded in various devices and services (mobile
phones, vital sign sensors, medication dispensers, home appliances,
engine ignition systems, etc). A large proportion of these systems
are mission/life critical and performance sensitive.

The 18th IEEE International Conference on Embedded and Real-Time
Computing Systems and Applications (RTCSA 2012) will bring together
researchers and developers from academia and industry for advancing
the technology of embedded and real-time systems, and ubiquitous
computing applications. The conference has the following goals: to
investigate advances in embedded and real-time systems and ubiquitous
computing applications; to promote interaction among the areas of
embedded computing, real-time computing and ubiquitous computing; to
evaluate the maturity and directions of embedded and real-time system
and ubiquitous computing technology. RTCSA 2012 invites submissions
of papers presenting a high quality original research and development
for the conference tracks: (1) Embedded Systems, (2) Real-time
Systems, and (3) Ubiquitous Computing/Cyber-physical Systems.

SCOPES: Following the tradition of RTCSA, the conference has three
tracks: embedded systems, real-time systems, and ubiquitous computing.
The topics of interest include, but are not limited to:

- System level design and HW/SW co-design
- Embedded system design practices
- Operating systems and scheduling
- Software and compiler issues for heterogeneous multi-core embedded
- Embedded system architecture
- Networks-on-chip design
- Power/thermal-aware design issues
- Memory issues for multi-core embedded platform
- Hardware and software techniques for fault tolerance
- Reconfigurable computing architecture and software support

- Real-time operating systems
- Real-time scheduling
- Timing analysis
- Databases
- Programming languages and run-time systems
- Middleware systems
- Design and analysis tools
- Communication networks and protocols
- Case studies and applications
- Media processing and transmissions
- Real-time aspects of Wireless sensor networks
- Energy aware real-time methods


- Real-time issues in ubiquitous computing and cyber-physical systems
- Tools, infrastructures and architectures for ubiquitous computing
and cyber-physical systems
- Devices and enabling technologies for ubiquitous computing and
cyber-physical systems
- Design and verification methodologies for cyber-physical systems
- Applications of wireless sensor networks
- Ubiquitous computing applications
- Cyber-physical systems applications
- User interfaces and interaction design issues for ubiquitous computing
- Privacy and security issues and implications of ubiquitous computing
- Location-dependent and context-aware computing
- Evaluation methods for ubiquitous computing devices, systems, and

Regular Paper Submission:

The submitted manuscript must describe original work not previously
published and not concurrently submitted elsewhere. Submissions
should be no more than 10 pages in IEEE conference proceedings format
(two-column, single-space, 10pt). The prospective authors should
submit their papers on RTCSA 2012 paper submission site: (in preparation for now)

Work-in-Progress Session:

This session provides an opportunity for researchers attending RTCSA
to present and discuss their research. This one hour event will
feature concurrent short presentations by all participants organized
in poster formats. More detailed information is available on the web.


Paper Submission: Apr 16, 2012, 12:00 (noon) GMT+9
Acceptance Notification: May 23, 2012
Camera Ready Submission: June 3, 2012

WIP Abstract Submission: June 18, 2012
WIP Notification: June 22, 2012
WIP Camerca Ready Submission: July 13, 2012

Early Registration Deadline: June 24, 2012


Steering Committee:
Tatsuo Nakajima, Waseda University, Japan (Chair)
Tei-Wei Kuo, National Taiwan University, Taiwan
Joseph K. Ng, Hong Kong Baptist University, China
Hide Tokuda, Keio University, Japan
Seongsoo Hong, Seoul National University, Korea
Sang H. Son, University of Virginia, USA

General Co-Chairs:
Yunheung Paek, Seoul National University, Korea
Jorgen Hansson, Chalmers University, Sweden

Program Co-Chairs:
Real-Time Systems: Steve Goddard, University of Nebraska-Lincoln, USA
Ubiquitous Comp/Cyber-Physical Systems: Chin-Fu Kuo, National University
of Kaohsiung, Taiwan
Embedded Systems: Jongeun Lee, UNIST, Korea

WIP Chair:
Chang-gun Lee, Seoul National University, Korea
Shinpei Kato, UC Santa Cruz, USA

Financial Chair:
Hyeonsang Eom, Seoul National University, Korea

Local Arrangement Chair:
Sung-Soo Lim, Kookmin University, Korea

Publication Chair:
Jangwoo Kim, Postech, Korea

Web Chair:
Neungsoo Park, Kunkuk University, Korea

Publicity Co-Chairs:
Thomas Nolte, Malardalen University, Sweden (Europe)
Yoshinori Takeuchi, Osaka University, Japan (Asia)
Sudeep Pasricha, Colorado State University, USA (USA)

Back to Contents

Call for Papers: International Conference on Very Large Scale Integration (VLSI-SOC)

20th IFIP/IEEE International Conference on Very Large Scale Integration
VLSI-SoC 2012
October 7-10, 2012
Santa Cruz, CA, USA
Dream Inn Hotel

VLSI-SoC 2012 is the 20th in a series of international conferences
sponsored by IFIP TC 10 Working Group 10.5, IEEE CEDA and IEEE CASS
that explores the state-of-the-art and the new developments in the
field of Very Large Scale Integration (VLSI) and System-on-Chip
(SoC). Previous Conferences have taken place in Edinburgh, Trondheim,
Tokyo, Vancouver, Munich, Grenoble, Gramado, Lisbon, Montpellier,
Darmstadt, Perth, Nice, Atlanta, Rhodes, Florianopolis, Madrid and
Hong Kong. The purpose of VLSI-SoC is to provide a forum to exchange
ideas, and show academia/industrial research results in the fields of
VLSI/ULSI Systems, SoC design, VLSI CAD and Microelectronic Design and

Topics of interest include but are not limited to:
* Analog and Mixed-Signal IC Design
* Circuits and Systems for Micro-sensing Applications
* 3-D Integration, Physical Design, Compact Modeling, and
Electromagnetic Analysis
* Design for Variability, Reliability, Fault Tolerance, Test
* Digital Signal Processing and Image Processing IC Design
* New Devices, MEMS and Microsystems
* Prototyping, Validation, Verification, Modeling and Simulation
* System-On-Chip Design, Digital Architectures
* Embedded Systems Design and Real-Time Systems
* Reconfigurable Systems, Compiler
* Logic and High-Level Synthesis
* Low-Power and Thermal-aware Design


Papers should present original research results not published or
submitted for publication in other forums. Electronic submission in
PDF format to the web site is required. The
proceedings will be published by IEEE and available through IEEE
Xplore. They will be distributed during the conference to all
participants. A selection of the conference best papers will be
invited to submit an extended version to be included as chapters of a
book to be published by Springer.

Paper Submission Deadline: April 9, 2012
Special Session Papers: April 23, 2012
Notification of acceptance: June 17, 2012
Camera-ready: July 11, 2012


Papers should not exceed 6 pages (single-spaced, 2 columns, 10pt
font). Submissions should be in camera-ready, following the IEEE
proceedings specifications located at:


Papers will be accepted for regular or poster presentation at the
conference. Every accepted paper MUST have at least one author
registered to the conference by the time the camera-ready paper is
submitted; the author is also expected to attend the conference and
present the paper. A limited number of travel grants are available to
needy PhD students. Please see the web site for more information.


The VLSI-SoC 2012's Ph.D. Forum is a poster session dedicated to the
exchange of ideas and experiences of Ph.D. students from different
parts of the world. Elected Ph.D. students have an opportunity to
discuss their thesis and research work with specialists within the
system and design automation communities. This exchange offers a good
opportunity for students to receive valuable feedback and gain
exposure in the job market. Furthermore, this forum also provides a
great chance for industry officials to meet junior researchers, giving
an avenue for incorporating the latest research developments into
their companies. More information in the conference web page.


1) Memristive Computing
Organizer: Sung-Mo (Steve) Kang, UC Santa Cruz, USA

Memristors and memristive devices have been recently realized in
nanoscale. Several recent implementations have brought forth the
potential for revolutions in non-volatile storage and reconfigurable
computing. This special session is specifically focused at using
memristive devices for computing in programmable systems such as

2) Open Source Tools and Methodologies for Research
Organizer: Jose Renau, UC Santa Cruz, USA

Open source tools enable both academia and industry to research,
develop, and share common platforms in complex research
tasks. However, most often these open source tools and methodologies
are unsung and, in fact, difficult to publish. This special session is
specifically focused at recognizing the most important and useful open
source tools and methodologies that aid research.

Special session papers should present original material not published
or submitted for publication in other forums. These papers will
undergo normal peer review. Electronic submission in PDF format to the web site is required.


General Chair:
Matthew Guthaus, UC Santa Cruz, USA

Program Chairs:
Ayse Coskun, Boston Univ., USA;
Andreas Burg, EPFL, Switzerland

Special Sessions Chair:
Sung-Mo "Steve" Kang, UC Santa Cruz, USA
Jose Renau, UC Santa Cruz, USA

Local Arrangement Chair:
Jose Renau, UC Santa Cruz, USA

Publication Chairs:
Srinivas Katkoori, Univ of South Florida, USA;
Ricardo Reis, UFRGS, Brazil

Publicity Chair:
Ricardo Reis, UFRGS, Brazil

Registration Chair:
Rajsaktish Sankaranarayanan, UC Santa Cruz, USA

Finance Chair:
Baris Taskin, Drexel, USA

PhD Forum Chair:
Ken Pedrotti, UC Santa Cruz, USA

Steering Committee:
Manfred Glesner, TU Darmstadt, Germany;
Salvador Mir, TIMA, France;
Ricardo Reis, UFRGS, Brazil;
Michel Robert, U. Montpellier, France;
Luis Miguel Silveira, INESC ID, Portugal


IFIP WG 10.5
IEEE Circuits and Systems Society
UC Santa Cruz

Back to Contents

Call for Papers: ACM Student Research Competition (SRC) at Design Automation Conference

Sponsored by Microsoft Research, the ACM Student Research Competition
is an internationally recognized venue enabling undergraduate and
graduate students who are ACM members to:

* Experience the research world -- for many undergraduates this is a
* Share research results and exchange ideas with other students,
judges, and conference attendees
* Rub shoulders with academic and industry luminaries
* Understand the practical applications of their research
* Perfect their communication skills
* Receive prizes and gain recognition from ACM and the greater
computing community.

The ACM Special Interest Group on Design Automation is organizing such
an event in conjunction with the Design Automation Conference. Authors
of accepted submissions will get travel grants from ACM/Microsoft to
attend the event at DAC. The event consists of several rounds, as
described at and , where you can also find more
details on student eligibility and timeline.

Details on abstract submission:

Research projects from all areas of design automation are
encouraged. The author submitting the abstract must still be a student
at the time the abstract is due. Each submission should be made on
the EasyChair submission site. Please include the author's name,
affiliation, postal address, and email address; research advisor's
name; ACM student member number; category (undergraduate or graduate);
research title; and an extended abstract (maximum 2 pages or 800
words) containing the following sections:

* Problem and Motivation: This section should clearly state the
problem being addressed and explain the reasons for seeking a
solution to this problem.
* Background and Related Work: This section should describe the
specialized (but pertinent) background necessary to appreciate the
work. Include references to the literature where appropriate, and
briefly explain where your work departs from that done by
others. Reference lists do not count towards the limit on the length
of the abstract.
* Approach and Uniqueness: This section should describe your approach
in attacking the problem and should clearly state how your approach
is novel.
* Results and Contributions: This section should clearly show how the
results of your work contribute to computer science and should
explain the significance of those results. Include a separate
paragraph (maximum of 100 words) for possible publication in the
conference proceedings that serves as a succinct description of the
* Note that submissions that are full thesis summaries should be sent
to the Ph.D. Forum and are not suitable for the ACM SRC@DAC. Single
paper summaries (or just cut & paste versions of published papers)
are also inappropriate for the ACM SRC. Submissions should include
at least one year worth of research contributions, but not
subsuming an entire doctoral thesis load.

Note that this event is different than other ACM/SIGDA sponsored or
supported events at DAC or ICCAD: YSSP brings together seniors and 1st
year graduate students at DAC, UBooth features demos from research
groups, DASS allows graduate students to get up to speed on lectures
on design automation, while the PhD Forum showcases post-proposal PhD
research at DAC and the CADathlon allows graduate students to compete
in a programming contest at ICCAD. The ACM Student Research
Competition allows both graduate and undergraduate students to discuss
their research with student peers, as well as academic and industry
researchers, in an informal setting, while enabling them to attend DAC
and compete with other ACM SRC winners from other computing areas in
the ACM Grand Finals. Travel grant recipients cannot receive travel
support from any other DAC or ACM/SIGDA sponsored program.

Important dates:

* Abstract submission deadline: April 8, 2012
* Acceptance notification: May 1, 2012
* Poster session at DAC: June 5, 2012
* Presentation session at DAC: June 6, 2012
* Award winners announced at DAC: June 7, 2012
* Grand Finals winners honored at ACM Awards Banquet: June 2013

Naehyuck Chang, Seoul National University
Srinivas Katkoori, University of South Florida

SPONSORED by Microsoft Research

Back to Contents

Call for Papers: Special Issue on Practical Parallel EDA

Call for Papers
IEEE Design & Test of Computers
Special Issue on Practical Parallel EDA

Guest Editors: Rasit O. Topaloglu (IBM) and Bevan M. Baas (University of California, Davis)

It is clear that future advances in computing performance will not be
driven by increases in individual core performance but rather by
factors such as an increasing number of available processors, or
specialized hardware. Thus, successful electronic design automation
(EDA) engineers and software developers must become familiar with
parallel algorithms and methods to exploit parallel and specialized
computing resources. Sequential EDA algorithms of the past are not
keeping pace with increasing design complexity—hence the striking need
to apply parallel computing methods to EDA problems.

Execution of software on parallel computing platforms requires a
re-engineering of EDA tools that are used during VLSI design. While
there are experts in various domains of parallelism, the knowledge has
yet to be dispersed widely and utilized in various EDA
tools. Attaining knowledge in parallelism requires one to understand
it from many aspects—for example, not only are parallel algorithms
typically different than serial ones, but the programming methods and
tools are also often significantly different. The availability of low
cost parallel processing hardware has made this transformation both
possible and increasingly relevant.

IEEE Design and Test Magazine is seeking contributions for a special
issue to educate engineers and present recent work in the area of
practical parallelism in EDA. Algorithm implementation can target
various parallel architectures such as: graphical processing units
(GPUs), multicore CPUs, manycore CPUs, distributed systems, advanced
processing units, and FPGAs. We also encourage submission of papers
that point to practical limitations of parallelism in EDA. Topics of
interest include but are not limited to:

* Parallel algorithms for electronic design automation
* Performance comparison of parallel programming methods for EDA algorithms2
* Performance comparison of parallel architectures for a given EDA
algorithm or set of algorithms.
* Performance comparison of EDA algorithms or set of algorithms
implemented on a variety of parallel architectures.
* Tips and tricks of parallel implementation from a real product
* User perspectives from parallel EDA software users
* Practical limitations of parallel EDA algorithm implementations
* Cost and benefit analysis of parallel EDA


Prospective authors should follow the submission guidelines for IEEE
Design & Test. All manuscripts must be submitted electronically to the
IEEE Manuscript Central Web site at . Indicate that you are
submitting your article to the special issue on Practical Parallel
EDA. All articles will undergo the standard IEEE Design & Test review
process. Submitted manuscripts must not have been previously published
or currently submitted for publication elsewhere. Manuscripts must not
exceed 5,000 words, including figures (with each average-size figure
counting as 200 words) and a maximum of 12 References (50 for
surveys). This amounts to about 4,000 words of text and a maximum of
five small to medium figures. Accepted articles will be edited for
clarity, structure, conciseness, grammar, passive to active voice,
logical organization, readability, and adherence to style. Please see
IEEE Design & Test Author Resources at, then scroll down and click on
Author Center for submission guidelines and requirements.


Articles due 4/15/2012
Reviews due 6/15/2012
Revisions due 7/15/2012
Final version due 9/1/2012
Publication 1-2/2013

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Call for Abstracts: International Workshop on Bio-Design Automation (IWBDA)


The Fourth International Workshop on Bio-Design Automation (IWBDA 2012)
San Francisco, June 3-4, 2012

The International Workshop on Bio-Design Automation (IWBDA) brings
together researchers from the synthetic biology, systems biology, and
design automation communities. The focus is on concepts,
methodologies, and software tools to enable the computational analysis
of biological systems and the synthesis of novel biological functions.

Tracks of interest include:

Design methodologies for synthetic biology
Standardization of biological components
Automated assembly techniques
Computer-aided modeling and abstraction techniques
Engineering methods inspired by biology
Domain specific languages for synthetic biology
Data exchange standards and models for synthetic biology

The workshop will be held at the Moscone Center in San Francisco on
June 3rd - 4th, 2012, co-located with the Design Automation Conference
(DAC). Registration information will be posted on the workshop
webpage: For questions, please


Abstracts should be two pages long, following the ACM SIG Proceedings
templates at Indicate
whether you would like your abstract considered for a poster
presentation, an oral presentation, or both. Include the full names,
affiliations and contact information of all authors.

Abstracts will be reviewed by the Program Committee. Those that are
selected for oral and poster presentations will distributed to
workshop participants and posted on the workshop website.

Abstracts should be submitted by April 2nd at:

Journal Special Issue
As in years past, we plan to have a special issue of a journal
associated with IWBDA. Details will be posted on the workshop website
when they become available.


Call for abstracts published: February 3rd, 2012
Abstract submission deadline: April 2nd, 2012
Abstract acceptance notification: May 7th, 2012
Workshop: June 3rd-4th, 2012


Jeff Hasty, UC San Diego
Jasmin Fisher, Microsoft, UK
William Shih, Harvard
Milan Stojanovic, Columbia


Natasa Miskov-Zivanov, University of Pittsburgh (General Chair)
Laura Adam, Virginia Tech (General Secretary)
Xiling Shen, Cornell (Program Committee co-Chair)
Deepak Chandran, University of Washington (Program Committee co-Chair)
Leonidas Bleris, University of Texas at Dallas (Program Committee co-Chair)
Smita Krishnaswamy, Columbia (DAC Liaison)
Chris Myers, University of Utah (Publication Chair)
Jonathan Babb, MIT (Industry/Government Funding Chair)
Aaron Adler, BBN Technologies (Finance co-Chair)
Fusun Yaman, BBN Technologies (Finance co-Chair)


J. Christopher Anderson, UC Berkeley
Adam Arkin, UC Berkeley
Jonathan Babb, MIT
Jacob Beal, BBN Technologies
Leonidas Bleris, UT Dallas
Kevin Clancy, Invitrogen
Douglas Densmore, Boston University
Drew Endy, Stanford
Abhishek Garg, Harvard University
Soha Hassou, Tufts
Mark Horowitz, Stanford
Alfonso Jaramillo, Ecole Polytechnique
Yannis Kaznessis, University of Minnesota
Eric Klavins, University of Washington
Tanja Kortemme, UCSF
Smita Krishnaswamy, Columbia
Natasa Miskov-Zivanov, University of Pittsburgh
Kartik Mohanram, Rice
Chris Myers, University of Utah
Andrew Phillips, Microsoft Research
Mark Riedel, University of Minnesota
Herbert Sauro, University of Washington
Xiling Shen, Cornell
David Thorsley, University of Washington
Christopher Voigt, UCSF
Ron Weiss, MIT
Erik Winfree, Caltech
Chris Winstead, Utah State University

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Call for Applications: Student Scholarships ACM A.M. Turing Centenary Celebration

Call for Applications
Student Scholarships ACM A.M. Turing Centenary Celebration

June 15 & 16 2012, Palace Hotel, San Francisco

June 23, 2012 marks the 100th anniversary of Alan Turing's birth. The
ACM A.M. Turing Award, given by ACM since 1966 in recognition of
contributions to computing and computer science, is widely held to be
the most prestigious award in computing. To celebrate the Turing
Centenary ACM is organizing a special event on Friday, June 15 and
Saturday, June 16, 2012.

The ACM A.M. Turing Centenary Celebration program centers on the ACM
A.M. Turing Award winners, thirty-three of whom will attend and
participate in the Celebration. The Technical Program includes
moderated panels and invited talks from select speakers and focuses on
Alan Turing's contributions, as well as the history, and the future of
computing. By bringing together so many ACM A.M. Turing Award winners
to reflect on Alan Turing's contribution and share their views on the
past and future of computing, the ACM A.M. Turing Centenary
Celebration will engage researchers, academics, students, and the
public in a conversation about the importance and direction of our

ACM SIGDA has a limited number of $1K scholarships (funded by Google,
Intel, Microsoft, and SIGDA) to award to worthy students to attend the
ACM Turing Centenary Celebration 15-16 June 2012 at the Palace Hotel
in San Francisco, CA. $500 of the scholarship must be used to cover 2
nights stay at the Palace Hotel. The remaining balance will go toward
travel expenses.

You should be a current ACM student member to apply for this
scholarship. Undergraduate and Graduate students are eligible to
apply. If you are an undergraduate, your department undergraduate
program director should endorse you. If you are a graduate student,
your research advisor or department graduate program director should
endorse you.

In order to be considered for the scholarship, email the following:
1. Completed application form (attached or download from here)
2. An endorsement by email from your advisor
3. Your resume (coursework with grades, any class/research
projects completed, prior accomplishments, honors/awards, etc.)

Email all requested material to by 5PM EST, Wednesday
4th April 2012.

Important Dates:
- Submission Deadline: 4 April 2012
- Notification of Awards: 11 April 2012
- ACM Turing Centenary Celebration 15-16 June 2012

If any questions, please contact Prof. Srinivas Katkoori at or (813) 974-5737.

Student Scholarship Application

Call for Applications

Back to Contents

Call for Papers: International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)


HiPEAC 2013: 8th International Conference on High-Performance and
Embedded Architectures and Compilers

January 21-23, 2013, Berlin, GERMANY

* Workshops/tutorials: June 1, 2012
* Papers: June 18, 2012
* Paper selection: November 15, 2012
* Posters: October 15, 2012

The HiPEAC conference is the premier scientific networking forum for
experts in computer architecture, programming models, compilers and
operating systems for embedded and general-purpose systems. Emphasis
is given on cross-cutting research and innovative ideas (new
programming models, novel architecture approaches, new technologies,
etc.). The conference hosts a number of associated workshops,
tutorials, a large poster session and an exhibition that run in
parallel with the conference. The 8th HiPEAC conference will take
place in Berlin, Germany from Monday 21 to Wednesday January 23, 2013.


In 2011, TACO and HiPEAC jointly carried out an experiment with a
publication model where original contributions on HiPEAC topics were
solicited for TACO. Record-high numbers of submitted and accepted
papers witness the significant interest in this model. This year, TACO
seeks original submissions at any time. Accepted TACO papers by
November 15, 2012 and whose topics match those of HiPEAC will be
selected and invited for presentation at HiPEAC conference. In order
to enjoy two rounds of review, and to be considered for invitation to
present at the HiPEAC 2013 conference, papers should be submitted no
later than June 18, 2012. Accepted papers will be published in
regular issues of ACM TACO.

For submission details, please refer to

Topics of interest to HiPEAC 2013 include, but are not limited to:

- Processor architectures
- Memory system optimization
- Power, performance and implementation efficient designs
- Reliability and real-time support in processors, compilers and
run-time systems
- Network and security processors
- Application-specific processors and accelerators
- Reconfigurable architectures
- Simulation and methodology
- Hardware and run-time support for programming languages
- Compiler techniques
- Feedback-directed optimization
- Program characterization and analysis techniques
- Dynamic compilation, adaptive execution, and continuous
- Binary translation/optimization
- Code size/memory footprint optimizations


HiPEAC 2013 General Chairs:
* Ben Juurlink (Technische Universität Berlin, Germany)
* Keshav Pingali (University of Texas Austin, USA)

Program Chairs:
* André Seznec (INRIA/IRISA, France)
* Lawrence Rauchwerger (Texas A&M University, USA)

Editor-in-chief of ACM Transactions on Architecture and Code Optimization:
* Tom Conte (Georgia Institute of Technology, USA)

Poster Chairs:
* Koen De Bosschere (Ghent University, Belgium)
* Qing Yi (University of San Antonio, USA)

Workshops/Tutorials Chair:
* Sascha Uhrig (Technische Universität Dortmund, Germany)

Industrial exhibit and European projects sub-committee:
* Henri-Pierre Charles (French Alternative Energies and Atomic Energy
Commission, France)
* Rosa M. Badia (Barcelona Supercomputing Center, Spain)

Publicity Chairs:
* Philip Brisk (U.C Riverside, USA)
* Nikola Puzovic (Barcelona Supercomputing Center, Spain)

Finance Chair:
* Jeroen Borghs (Ghent University, Belgium)

Submission Chair:
* Michiel Ronsse (Ghent University, Belgium)

Web and Registrations Chair:
* Klaas Millet (Ghent University, Belgium)

Local organizing committee:
* Nico Moser (Technische Universität Berlin, Germany)
* Paula Herber (Technische Universität Berlin, Germany)
* Reinier van Kampenhout (Fraunhofer FIRST, Germany)

Steering Committee:
* Anant Agarwal (MIT, USA)
* Koen De Bosschere (Ghent University, Belgium)
* Albert Cohen (INRIA, France)
* Tom Conte (Georgia Institute of Technology, USA)
* Wen-mei W. Hwu (UIUC, USA)
* Walid Najjar (UC Riverside, USA)
* Per Stenstrom (Chalmers University, Sweden, Chair)
* Theo Ungerer (University of Augsburg, Germany)
* Mateo Valero (UPC, Spain)

Back to Contents

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